In a computer system having multiple processors connected by a network of point to point bit-serial links, the point to point links may operate in burst mode--e.g.. to save power. In this case, idle symbols are not transmitted as filler when there is no useful data to be transmitted. Accordingly, at the beginning of each newly received burst, a receiver must establish a correct phase relationship between the data stream and the receiver clock. i.e. the receiver must sample the incoming data stream at the frequency of the incoming data and within a defined range of phase to avoid an unacceptable error rate. The general approach to achieving proper phasing for sampling in the prior art is to create an internal reference clock within the receiver, synchronized to the frequency and phase of the incoming data. The process of synchronizing an internal reference clock with an incoming data stream is known as "clock recovery".
A conventional clock recovery method involves the use of a phase-locked loop (PLL). The PLL is essentially a phase detector and an oscillator in a feedback loop configuration. The phase detector compares the input signal (data) to the output of the oscillator and generates a control signal that varies with the phase difference. The phase of the oscillator's output is controlled by the output of the phase detector. The phase comparison and output phase adjustment process drives the oscillator's output to match (lock) to the phase of the input signal (data).
Until recently, PLL circuits have been implemented with analog technology. Implementing an analog PLL on an otherwise digital circuit presents several disadvantages. Early digital clock recovery circuits (sometimes called digital phase-locked loops) operate at frequencies much higher than the "recovered" clock-in fact, typically one to two orders of magnitude higher. These circuits severely limit the communication performance available from any given semiconductor technology. In the 1980's, digital clock recovery circuits operating at the same frequency as the recovered clock began to appear.
The following three patents disclose digital PLL's that support high data rate capability. Each of these digital PLL's assumes an incoming data stream of the same (or nearly the same) frequency as its reference clock, and produces a clock phase-locked to the data stream. All three synchronize over a relatively narrow range of frequencies.
U.S. Pat. No. 4,789,996, issued to Butcher on Dec. 6, 1988 discloses a center frequency high resolution digital phase-lock loop circuit. The receivers's reference clock is fed through an N-tap delay line where N.gtoreq.(TREF/minimum tap propagation delay). Each tap introduces a fixed time delay. An N-bit left/right shift register is used to "switch in" the number of taps the reference clock travels through, and thus the amount of phase shift introduced. The phase detector compares the incoming data to the PLL output clock. Based on the output of the phase detector, a control circuit sends "shift left", "shift right", or "hold" commands to the shift register that advance, retard, or maintain the phase, respectively. The L/R shift register is adjusted one position at a time until a "stable" state is found. The maximum "settling time" is N+10 clock periods. Note that this is not a purely digital circuit. The 180 degree inhibit circuit uses an RC network. Butcher states that an all-digital inhibit circuit would not work as well (column 8, lines 7-9). The Butcher disclosure describes the basic concept of a digital PLL that employs a tapped delay line.
U.S. Pat. No. 4,819,251, issued to Nelson on Apr. 4, 1989, discloses a high speed non-return-to-zero digital clock recovery circuit. The Nelson circuit also uses an N-tap (N=10) delay line. In Nelson, the tapped delay line is used to produce delayed versions of a clock-in other words, different phases of the clock. It has a phase detector circuit which samples the incoming data with every delayed clock (i.e., there are 10 data samples). The phase detector counts how many of the 10 data samples transition from zero to one between the occurrence of a rising (logic zero to one) edge in the incoming data and rising edge in the oscillator output. This transition sum reflects the phase difference between the incoming data and the PLL output clock. The sum is compared to an upper and lower bound, and if not within the specified range, increment or decrement signals are generated that advance or retard, respectively, the phase of the oscillator's output. The PLL output is then used to sample the data.
U.S. Pat. No. 5,040,193, issued to Leonowich et al. on Aug. 13, 1991, discloses a receiver and digital phase-locked loop for burst mode data. In the Leonowich receiver, the reference clock (not the data) is fed into the delay line. Preferably, the delay line provides at least one clock period (T) of delay. All N tap outputs are fed to an N:1 multiplexer. The output of this multiplexer is the PLL clock output. The single synchronous transition detector (STD) compares the incoming data to the output clock, determining whether either a falling or rising edge has occurred in the data during the time the output clock is at a logic high level. It appears that half the clock cycle is used because the incoming data is Manchester encoded. All N cells of the "interlocked coincidence detector" (ICD) receive the ICD output as well as one of the delayed clocks. Each ICD cell checks whether the delayed clock it receives from the delay line is low or goes low during the time the ICD signal is active (again, active for at most one-half a clock cycle). The "interlocked" part of the name comes from the fact that only one cell's output can be active at a time--a cell can only have an active output if the previous cell in the chain has an inactive output: an active cell output disables the outputs of all cells "further down the line". The outputs from all the ICD cells form an N-bit word that is subtracted from the number of the currently selected tap: this difference is the phase difference/adjustment. Phase adjustment are enabled during reception of a frame's preamble, and disabled at all other times. A multiplexer switches in a high "loop gain" for faster lock, then a lower gain once lock is established.
There appear, in the prior art, to be no all-digital solutions to the clock synchronization problem that offer high data rate capability and also accommodate a wide range of data rates.